1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device that supports a test mode accessible from the exterior.
2. Description of the Related Art
A synchronous semiconductor memory device uses a mode register and a mode register set (MRS). The mode register programs and stores data for controlling various operation modes of the synchronous semiconductor memory device.
The operation modes or characteristics of a conventional semiconductor memory device are decided by an inputted control signal. However, in the synchronous semiconductor memory device, a central processing unit (CPU) presets an operation mode of the synchronous semiconductor memory device to be used later, that is, CAS latency (column address strobe latency) or a burst length, and accesses the synchronous semiconductor memory device. Such an operation mode is set and stored in the mode register, and a set of a series of mode registers is called a mode register set (MRS). Accordingly, a series of codes indicating the modes of a semiconductor memory device are set in the mode register set, wherein such codes are called MRS (mode register set) codes.
Conventionally, the MRS codes are generated by a combination of addresses. The MRS codes are generated by the combination of addresses and respective operation modes of a semiconductor memory device are decided corresponding to the generated MRS codes. Such MRS codes are standardized by JEDEC. MRS codes for testing a semiconductor memory device designed in a semiconductor design process are necessary, which are called test MRS codes.
FIG. 1 is a table of MRS codes of a semiconductor memory device according to the conventional art.
Referring to FIG. 1, table values of the MRS codes are decided by a combination of signals applied through address pads BA2 to BA0 and A15 to A0.
In detail, among the signals inputted through the address pads BA2 to BA0 and A15 to A0, a signal TM of the address pad A7 is used in order to control entrance to a test mode of the semiconductor memory device. That is, the semiconductor memory device performs a normal operation when the value of the signal TM is ‘0’, and performs a test mode operation when the value of the signal TM is ‘1’.
When the value of the signal TM is ‘1’ and the semiconductor memory device performs the test mode operation, methods for inputting test operation codes used in a test mode to the semiconductor memory device differ between fabricating companies of the semiconductor memory device. That is, since detailed internal operations of the semiconductor memory device differ between the fabricating companies and methods for testing the operations are very complicated, the test methods performed on the semiconductor memory device are not accessible from the exterior of the semiconductor memory device.
As many functions are added to the semiconductor memory device, including timing adjustments and the like, to obtain high speed operation, it is highly necessary for an external semiconductor controller or user to perform specific common test functions of the semiconductor memory device. However, since semiconductor companies are concerned with security and compete to guarantee product operation, test mode operation methods necessary for development and testing are kept in secret and not generally open to the public. It is highly probable that defining a specific function or timing through a separate specification (SPEC.), by using MRS codes for the release, faces limitations when considering the growing types of necessary test modes. [Revised the paragraph to improve clarity. Please verify. Thank you.]
In this regard, it is necessary to provide a method for allowing an external semiconductor controller or user to access some internal test mode operations that may be open in the range of the specification (SPEC.) of a semiconductor memory device.